Simultaneous switching noise (SSN) from an aggressor input/output (I/O) pin in a device will impact nearby or proximate victim I/O pins of an electronic component because of the switching from the aggressor I/O pin. Attempts to characterize the SSN impact have not yielded robust techniques especially with regard to multiple I/O standards. Modeling the SSN behavior of a device is a difficult task in general. This problem is exacerbated further when dealing with a programmable logic device (PLD), such as a field programmable gate array (FPGA). It should be appreciated that due to the FPGA's support of numerous I/O standards, modes, and drive strengths, the problem becomes much more complex. Because of the flexibility of an FPGA it becomes nearly impossible to measure SSN noise for every possible I/O configuration combination. One of the shortcomings of prior attempts is the fact that these attempts have not considered the cumulative impact of the number of pins, or the cumulative impact of the noise from previously assigned pins, on pins to be assigned.
Accordingly, there is a need to measure SSN noise individually for each I/O standard and to use this data to estimate the SSN noise performance of the mixed I/O standards case.